NXP Semiconductors /MIMXRT1052 /IOMUXC /SW_MUX_CTL_PAD_GPIO_AD_B1_09

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Interpret as SW_MUX_CTL_PAD_GPIO_AD_B1_09

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

SION=DISABLED, MUX_MODE=ALT0

Description

SW_MUX_CTL_PAD_GPIO_AD_B1_09 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: FLEXSPIA_DQS of instance: flexspi

1 (ALT1): Select mux mode: ALT1 mux port: FLEXPWM4_PWMA01 of instance: flexpwm4

2 (ALT2): Select mux mode: ALT2 mux port: FLEXCAN1_RX of instance: flexcan1

3 (ALT3): Select mux mode: ALT3 mux port: SAI1_MCLK of instance: sai1

4 (ALT4): Select mux mode: ALT4 mux port: CSI_DATA08 of instance: csi

5 (ALT5): Select mux mode: ALT5 mux port: GPIO1_IO25 of instance: gpio1

6 (ALT6): Select mux mode: ALT6 mux port: USDHC2_CLK of instance: usdhc2

7 (ALT7): Select mux mode: ALT7 mux port: KPP_COL03 of instance: kpp

SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_AD_B1_09

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